Search - filter fir vhdl

[VHDL-FPGA-Verilog] fir.tar

Description: FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
Platform: | Size: 4096 | Author: 王晓东 | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] FIR_beh

Description: FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
Platform: | Size: 1024 | Author: 郭兴波 | Hits:

[VHDL-FPGA-Verilog] fir-vhdl

Description: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Platform: | Size: 5120 | Author: MAX | Hits:

[Software Engineering] filter-vhdl-code

Description: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, including an integrated code. Use version ISE6.3.
Platform: | Size: 173056 | Author: petri | Hits:

[VHDL-FPGA-Verilog] fir

Description: FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
Platform: | Size: 173056 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] fir

Description: 滤波器的vhdl实现滤波器的vhdl实现-Filter VHDL VHDL realization of filters to achieve
Platform: | Size: 1024 | Author: 阿乔 | Hits:

[DSP program] FIR

Description: 用DSP BUILDER设计的3阶和四阶滤波器-DSP BUILDER designed with 3-order and fourth-order filter
Platform: | Size: 18432 | Author: gillyamylee | Hits:

[VHDL-FPGA-Verilog] DecimationFilterDesignforDDCandImplementingItwithF

Description: 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性-This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design
Platform: | Size: 468992 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR数字滤波器分布式算法的原理及FPGA实现-Distributed Arithmetic FIR digital filter FPGA Principle and realize
Platform: | Size: 599040 | Author: 王杰 | Hits:

[Documents] fir

Description: 线性相位FIR滤波器（17阶）的VHDL语言设计功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Platform: | Size: 148480 | Author: jingjing | Hits:

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[VHDL-FPGA-Verilog] fir.tar

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

[Button control] 4yue11haoxiawu

[VHDL-FPGA-Verilog] firISPdesign

[VHDL-FPGA-Verilog] FIR_beh

[VHDL-FPGA-Verilog] fir-vhdl

[Software Engineering] filter-vhdl-code

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] fir

[DSP program] FIR

[VHDL-FPGA-Verilog] DecimationFilterDesignforDDCandImplementingItwithF

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] FIR

[Documents] fir

[VHDL-FPGA-Verilog] VHDLFIR

[Software Engineering] bandpass-filter

[Mathimatics-Numerical algorithms] fir_rtl

[VHDL-FPGA-Verilog] fir-vhdl-code

[VHDL-FPGA-Verilog] FIR-filter-vhdl

[VHDL-FPGA-Verilog] FIR-filter-using-fpga-design

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